UPD78F0411GA-GAM-AX Datasheet, PDF (476/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 20 RESET FUNCTION
Table 20-1. Operation Statuses During Reset Period
Item
During Reset Period
System clock
Clock supply to the CPU is stopped.
Main system clock fRH
Operation stopped
fX
Operation stopped (pin is I/O port mode)
fEXCLK Clock input invalid (pin is I/O port mode)
Subsystem clock fXT
Operation stopped (pin is I/O port mode)
fRL
Operation stopped
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
00
counter
8-bit timer/event
50
counter
51
52
8-bit timer
H0
H1
H2
Real-time counter
Watchdog timer
Buzzer output
10-bit successive approximation
type A/D converter^Note
Serial interface UART0
UART6
LCD controller/driver
Manchester code generator
Power-on-clear function
Operable
Low-voltage detection function Operation stopped
External interrupt
Note μPD78F041x only.
Remark
fRH:
fX:
fEXCLK:
fXT:
fRL:
Internal high-speed oscillation clock
X1 oscillation clock
External main system clock
XT1 oscillation clock
Internal low-speed oscillation clock
474
User’s Manual U18698EJ1V0UD