UPD78F0411GA-GAM-AX Datasheet, PDF (299/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only)
Figure 12-5. A/D Converter Sampling and A/D Conversion Timing
ADCS ← 1 or ADS rewrite
ADCS
Sampling
timing
INTAD
Wait SAR
period^Note clear
Sampling
Successive conversion Transfer SAR
to ADCR, clear
INTAD
generation
Sampling
Conversion time
Conversion time
Note For details of wait period, see CHAPTER 29 CAUTIONS FOR WAIT.
(2) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The lower 6 bits are fixed to 0. Each time
A/D conversion ends, the conversion result is loaded from the successive approximation register. The higher 8
bits of the conversion result are stored in FF07H and the lower 2 bits are stored in the higher 2 bits of FF06H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 12-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Address: FF06H, FF07H After reset: 0000H R
Symbol
FF07H
FF06H
ADCR
0
0
0
0
0
0
Cautions 1. When writing to the A/D converter mode register (ADM), analog input channel specification
register (ADS), and A/D port configuration register 0 (ADPC0), the contents of ADCR may
become undefined. Read the conversion result following conversion completion before
writing to ADM, ADS, and ADPC0. Using timing other than the above may cause an incorrect
conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
CPU is operating on the subsystem clock and the peripheral hardware clock is stopped. For
details, see CHAPTER 29 CAUTIONS FOR WAIT.
User’s Manual U18698EJ1V0UD
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