UPD78F0411GA-GAM-AX Datasheet, PDF (74/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
Register pair contents specified by a register pair specify code in an instruction word and by a register bank
select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be
carried out for all of the memory spaces.
[Operand format]
Identifier
−
[DE], [HL]
Description
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
10000101
[Illustration]
16
DE
D
The contents of the memory
addressed are transferred.
7
A
87
0
E
7
Memory
0
0
The memory address
specified with the
register pair DE
72
User’s Manual U18698EJ1V0UD