UPD78F0411GA-GAM-AX Datasheet, PDF (193/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
Figure 6-42. Example of Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
TMC003 TMC002 TMC001 OVF00
0
0
0
0
1
1
0
0
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
CRC002 CRC001 CRC000
0
0
0
0
0
0
0
0
CR000 used as
compare register
CR010 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
0
0
0
1
0/1
0/1
1
1
(d) Prescaler mode register 00 (PRM00)
ES101 ES100 ES001 ES000
3
0
0
0
0
0
Enables TO00 output
Specifies initial value of
TO00 output F/F
11: Inverts TO00 output on
match between TM00
and CR000/CR010.
00: Disables one-shot pulse
output
PRM002 PRM001 PRM000
0/1
0/1
0/1
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
Selects count clock
(f) 16-bit capture/compare register 000 (CR000)
An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00.
The count value of TM00 is not cleared.
(g) 16-bit capture/compare register 010 (CR010)
An interrupt signal (INTTM010) is generated when the value of this register matches the count value of TM00.
The count value of TM00 is not cleared.
Caution Set values to CR000 and CR010 such that the condition 0000H ≤ CR010 < CR000 ≤ FFFFH is
satisfied.
User’s Manual U18698EJ1V0UD
191