UPD78F0411GA-GAM-AX Datasheet, PDF (489/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 22 LOW-VOLTAGE DETECTOR
Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
Address: FFBEH After reset: 00H^{Note 1} R/W^{Note 2}
Symbol
<7>
6
5
4
LVIM
LVION
0
0
0
3
<2>
<1>
<0>
0
LVISEL LVIMD
LVIF
LVION^{Notes 3, 4}
0
Disables operation
1
Enables operation
Enables low-voltage detection operation
LVISEL^{Note 3}
Voltage detection selection
0
Detects level of supply voltage (VDD)
1
Detects level of input voltage from external input pin (EXLVI)
LVIMD^{Note 3}
Low-voltage detection operation mode (interrupt/reset) selection
0
• LVISEL = 0: Generates an internal interrupt signal when the supply voltage (VDD) drops
lower than the detection voltage (VLVI) (VDD < VLVI) or when VDD becomes
VLVI or higher (VDD ≥ VLVI).
• LVISEL = 1: Generates an interrupt signal when the input voltage from an external
input pin (EXLVI) drops lower than the detection voltage (VEXLVI) (EXLVI <
VEXLVI) or when EXLVI becomes VEXLVI or higher (EXLVI ≥ VEXLVI).
1
• LVISEL = 0: Generates an internal reset signal when the supply voltage (VDD) <
detection voltage (VLVI) and releases the reset signal when VDD ≥ VLVI.
• LVISEL = 1: Generates an internal reset signal when the input voltage from an
external input pin (EXLVI) < detection voltage (VEXLVI) and releases the
reset signal when EXLVI ≥ VEXLVI.
LVIF
0
1
Low-voltage detection flag
• LVISEL = 0: Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is
disabled
• LVISEL = 1: Input voltage from external input pin (EXLVI) ≥ detection voltage (VEXLVI),
or when operation is disabled
• LVISEL = 0: Supply voltage (VDD) < detection voltage (VLVI)
• LVISEL = 1: Input voltage from external input pin (EXLVI) < detection voltage (VEXLVI)
Notes 1.
2.
3.
4.
This bit is cleared to 00H upon a reset other than an LVI reset.
Bit 0 is read-only.
LVION, LVIMD, and LVISEL are cleared to 0 in the case of a reset other than an LVI reset.
These are not cleared to 0 in the case of an LVI reset.
When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to wait for an operation stabilization time (10 μs (MAX.)) from when LVION is set to 1
until operation is stabilized. After operation has stabilized, 200 μs (MIN.) are required from
when a state below LVI detection voltage has been entered, until LVIF is set (1).
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD.
3. When using LVI as an interrupt, if LVION is cleared (0) in a state below the LVI
detection voltage, an INTLVI signal is generated and LVIIF becomes 1.
User’s Manual U18698EJ1V0UD
487