UPD78F0411GA-GAM-AX Datasheet, PDF (213/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
(2) Cautions for input enable control for TI52 pin
The input enable control signal (TMH2 output signal) for the TI52 pin is synchronized by the TI52 pin input clock,
as described in Figure 6-54 Configuration Diagram of External 24-bit Event Counter and Figure 6-55
Operation Timing of External 24-bit Event Counter. Thus, when the counter is operated as an external event
counter, an error up to one count may be caused.
(3) Cautions for 16-bit timer/event counter 00 count up during external 24-bit event counter operation
16-bit timer/event counter 00 has an internal synchronization circuit to eliminate noise when starting operation,
and the first clock immediately after operation start is not counted.
When using the counter as a 24-bit counter, by setting 16-bit timer/event counter 00 and 8-bit timer/event counter
52 as the higher and lower timer and connecting them in cascade, the interrupt request flag of 8-bit timer/event
counter 52 which is the lower timer must be checked as described below, in order to accurately read the 24-bit
count values.
- If TMIF52 = 1 when TM52 and TM00 are read:
The actual TM00 count value is “read value of TM00 + 1”.
- If TMIF52 = 0 when TM52 and TM00 are read:
The read value is the correct value.
This phenomenon of 16-bit timer/event counter 00 occurs only when operation is started. A count delay will not
occur when 16-bit timer/event counter 00 overflows and the count is restarted from 0000H, since synchronization
has already been implemented.
<When starting operation>
TM52 00H
01H 02H
TM00 0000H 0000H 0000H
TMIF52
when timer operation is started
<Overflow of higher timer>
FFH 00H 01H
0000H 0000H 0000H
FFH 00H 01H
0000H 0001H 0001H
The timer does not count up
The timer counts up upon second
upon the first overflow of TM52. and subsequent overflows.
TM52 FFH
00H 01H
TM00 FFFFH 0000H 0000H
FFH 00H 01H
0000H 0001H 0001H
FFH 00H 01H
0001H 0002H 0002H
Overflow
The timer counts up as normal
upon an overflow of TM00.
User’s Manual U18698EJ1V0UD
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