UPD78F0411GA-GAM-AX Datasheet, PDF (226/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52
Figure 7-8. Format of Timer Clock Selection Register 52 (TCL52)
Address: FF5BH After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
TCL52
0
0
0
0
0
TCL522 TCL521 TCL520
TCL522
0
0
0
0
1
1
1
1
TCL521
0
0
1
1
0
0
1
1
TCL520
0
1
0
1
0
1
0
1
Count clock selection^Note1
fPRS =
2 MHz
fPRS =
5 MHz
Falling edge of clock selected by ISC2
Rising edge of clock selected by ISC2
f ^Note2
PRS
2 MHz
5 MHz
fPRS/2
fPRS/2⁴
fPRS/2⁶
fPRS/2⁸
fPRS/2¹²
1 MHz
125 kHz
31.25 kHz
7.81 kHz
0.49 kHz
2.5 MHz
312.5 kHz
78.13 kHz
19.53 kHz
1.22 kHz
fPRS =
10 MHz
10 MHz
5 MHz
625 kHz
156.25 kHz
39.06 kHz
2.44 kHz
Notes 1.
2.
If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
If the peripheral hardware clock (fPRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of TCL522, TCL521, TCL520 = 0, 1, 0 (count clock: fPRS) is
prohibited.
Cautions 1. When rewriting TCL52 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.
Remark fPRS: Peripheral hardware clock frequency
224
User’s Manual U18698EJ1V0UD