UPD78F0411GA-GAM-AX Datasheet, PDF (192/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.4.6 PPG output operation
A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG
(Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-
bit timer mode control register 00 (TMC00) are set to 11 (clear & start upon a match between TM00 and CR000).
The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
• Pulse cycle = (Set value of CR000 + 1) × Count clock cycle
• Duty = (Set value of CR010 + 1) / (Set value of CR000 + 1)
Caution To change the duty factor (value of CR010) during operation, see 6.5.1 Rewriting CR010 during
TM00 operation.
Remarks 1. For the setting of I/O pins, see 6.3 (6) Port mode register 3 (PM3).
2. For how to enable the INTTM000 signal interrupt, see CHAPTER 17 INTERRUPT FUNCTIONS.
Figure 6-41. Block Diagram of PPG Output Operation
Count clock
Operable bits
TMC003, TMC002
Clear
Timer counter
(TM00)
Match signal
Compare register
(CR000)
Match signal
Compare register
(CR010)
Output
controller
Interrupt signal
(INTTM000)
TO00
output
TO00 pin
Interrupt signal
(INTTM010)
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User’s Manual U18698EJ1V0UD