UPD78F0411GA-GAM-AX Datasheet, PDF (552/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
AC Characteristics
Standard products
(1) Basic operation
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
MIN. TYP.
Instruction cycle (minimum
TCY
Main system clock (fXP)
instruction execution time)
operation
2.7 V ≤ VDD ≤ 5.5 V 0.2
1.8 V ≤ VDD < 2.7 V 0.4
Subsystem clock (fSUB) operation
114 122
Peripheral hardware clock
frequency
fPRS
XSEL = 1 2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
XSEL = 0 2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V^{Note 1}
7.6
6.75
External main system clock
fEXCLK
2.7 V ≤ VDD ≤ 5.5 V
2.0
frequency
1.8 V ≤ VDD < 2.7 V
2.0
External main system clock
tEXCLKH, 2.7 V ≤ VDD ≤ 5.5 V
48
input high-level width, low-level tEXCLKL _{1.8 V ≤ VDD < 2.7 V}
96
width
TI000 input high-level width,
low-level width
tTIH0,
tTIL0
2.7 V ≤ VDD ≤ 5.5 V
2/fsam +
0.2^{Note 2}
1.8 V ≤ VDD < 2.7 V
2/fsam +
0.5^{Note 2}
TI52 input frequency
fTI5
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
1.8 V ≤ VDD < 2.7 V
TI52 input high-level width, low- tTIH5,
level width
tTIL5
4.0 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.0 V
31.25
50
1.8 V ≤ VDD < 2.7 V
100
Interrupt input high-level width, tINTH,
1
low-level width
tINTL
Key return input low-level width tKR
250
RESET low-level width
tRSL
10
MAX.
16
16
125
10
5
8.4
8.4
10.0
5.0
500
500
16
10
5
Unit
μs
μs
μs
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
μs
μs
MHz
MHz
MHz
ns
ns
ns
μs
ns
μs
Notes 1.
2.
A characteristic of the main system clock frequency. Set the clock divider to be set using a peripheral
function to fRH/2 or less.
Selection of fsam = fPRS, fPRS/4, fPRS/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler
mode registers 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fPRS.
550
User’s Manual U18698EJ1V0UD