UPD78F0411GA-GAM-AX Datasheet, PDF (114/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
CPU Clock (fCPU)
fXP
fXP/2
fXP/2²
fXP/2³
fXP/2⁴
fSUB/2
Minimum Instruction Execution Time: 2/fCPU
Main System Clock
High-Speed System Clock^Note
Internal High-Speed
Oscillation Clock^Note
Subsystem Clock
At 10 MHz Operation
At 8 MHz (TYP.) Operation
At 32.768 kHz Operation
0.2 μs
0.25 μs (TYP.)
−
0.4 μs
0.5 μs (TYP.)
−
0.8 μs
1.0 μs (TYP.)
−
1.6 μs
2.0 μs (TYP.)
−
3.2 μs
4.0 μs (TYP.)
−
−
−
122.1 μs
Note The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (high-
speed system clock/internal high-speed oscillation clock) (see Figure 5-6).
(3) Setting of operation mode for subsystem clock pin
The operation mode for the subsystem clock pin can be set by using bit 4 (OSCSELS) of the clock operation
mode select register (OSCCTL) in combination.
Table 5-3. Setting of Operation Mode for Subsystem Clock Pin
Bit 4 of OSCCTL
OSCSELS
0
1
Subsystem Clock Pin
Operation Mode
Input port mode
XT1 oscillation mode
P123/XT1 Pin
P124/XT2 Pin
Input port
Crystal resonator connection
Caution Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating
with main system clock) when changing the current values of OSCSELS.
112
User’s Manual U18698EJ1V0UD