UPD78F0411GA-GAM-AX Datasheet, PDF (218/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
(7) Operation of OVF00 flag
(a) Setting OVF00 flag (1)
The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows.
Select the clear & start mode entered upon a match between TM00 and CR000.
↓
Set CR000 to FFFFH.
↓
When TM00 matches CR000 and TM00 is cleared from FFFFH to 0000H
Figure 6-61. Operation Timing of OVF00 Flag
Count pulse
CR000 FFFFH
TM00 FFFEH
FFFFH 0000H 0001H
OVF00
INTTM000
(b) Clearing OVF00 flag
Even if the OVF00 flag is cleared to 0 after TM00 overflows and before the next count clock is counted
(before the value of TM00 becomes 0001H), it is set to 1 again and clearing is invalid.
(8) One-shot pulse output
One-shot pulse output operates correctly in the free-running timer mode or the clear & start mode entered by the
TI000 pin valid edge. The one-shot pulse cannot be output in the clear & start mode entered upon a match
between TM00 and CR000.
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User’s Manual U18698EJ1V0UD