UPD78F0411GA-GAM-AX Datasheet, PDF (152/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
Address: FFBAH After reset: 00H R/W
Symbol
7
6
5
TMC00
0
0
0
4
3
2
1
0
TMC003
TMC002
TMC001
<0>
OVF00
TMC003
0
0
1
1
TMC002
0
1
0
1
Operation enable of 16-bit timer/event counter 00
Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock.
Clears 16-bit timer counter 00 (TM00).
Free-running timer mode
Clear & start mode entered by TI000 pin valid edge input^Note
Clear & start mode entered upon a match between TM00 and CR000
TMC001
0
1
Condition to reverse timer output (TO00)
• Match between TM00 and CR000 or match between TM00 and CR010
• Match between TM00 and CR000 or match between TM00 and CR010
• Trigger input of TI000 pin valid edge
OVF00
TM00 overflow flag
Clear (0) Clears OVF00 to 0 or TMC003 and TMC002 = 00
Set (1) Overflow occurs.
OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match
between TM00 and CR000).
It can also be set to 1 by writing 1 to OVF00.
Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).
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User’s Manual U18698EJ1V0UD