UPD78F0411GA-GAM-AX Datasheet, PDF (537/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 26 INSTRUCTION SET
Instruction
Mnemonic
Group
Operands
Bit
AND1
manipulate
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
OR1
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
XOR1
CY, saddr.bit
CY, sfr.bit
CY, A.bit
SET1
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
CLR1
SET1
CLR1
NOT1
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Bytes
Clocks
Note 1 Note 2
Operation
3
6
7 CY ← CY ∧ (saddr.bit)
3
−
7 CY ← CY ∧ sfr.bit
2
4
− CY ← CY ∧ A.bit
3
−
7 CY ← CY ∧ PSW.bit
2
6
7 CY ← CY ∧ (HL).bit
3
6
7 CY ← CY ∨ (saddr.bit)
3
−
7 CY ← CY ∨ sfr.bit
2
4
− CY ← CY ∨ A.bit
3
−
7 CY ← CY ∨ PSW.bit
2
6
7 CY ← CY ∨ (HL).bit
3
6
7 CY ← CY ∨ (saddr.bit)
3
−
7 CY ← CY ∨ sfr.bit
2
4
− CY ← CY ∨ A.bit
3
−
7 CY ← CY ∨ PSW.bit
2
6
7 CY ← CY ∨ (HL).bit
2
4
6 (saddr.bit) ← 1
3
−
8 sfr.bit ← 1
2
4
− A.bit ← 1
2
−
6 PSW.bit ← 1
2
6
8 (HL).bit ← 1
2
4
6 (saddr.bit) ← 0
3
−
8 sfr.bit ← 0
2
4
− A.bit ← 0
2
−
6 PSW.bit ← 0
2
6
8 (HL).bit ← 0
1
2
− CY ← 1
1
2
− CY ← 0
1
2
− CY ← CY
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×××
×××
1
0
×
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
User’s Manual U18698EJ1V0UD
535