UPD78F0411GA-GAM-AX Datasheet, PDF (252/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
<4> When the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output and the compare
register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n
register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.
<6> To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count
clock frequency is fCNT, the PWM pulse output cycle and duty are as follows.
• PWM pulse output cycle = (N + 1)/fCNT
• Duty = (M + 1)/(N + 1)
Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating.
However, this takes a duration of three operating clocks (signal selected by the CKSn2 to
CKSn0 bits of the TMHMDn register) from when the value of the CMP1n register is changed
until the value is transferred to the register.
2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after
the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to the CMP1n register).
3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Remarks 1. For the setting of the output pin, see 8.3 (3) Port mode register 3 (PM3).
2. For details on how to enable the INTTMHn signal interrupt, see CHAPTER 17
FUNCTIONS.
3. n = 0 to 2, however, TOH0 and TOH1 only for TOHn
INTERRUPT
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User’s Manual U18698EJ1V0UD