UPD78F0411GA-GAM-AX Datasheet, PDF (329/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 13 SERIAL INTERFACE UART0
(c) Transmission
If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6
(TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit
data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to
the data.
When transmission is started, the start bit is output from the TXD0 pin, and the transmit data is output
followed by the rest of the data in order starting from the LSB. When transmission is completed, the parity
and stop bits set by ASIM0 are appended and a transmission completion interrupt request (INTST0) is
generated.
Transmission is stopped until the data to be transmitted next is written to TXS0.
Figure 13-9 shows the timing of the transmission completion interrupt request (INTST0). This interrupt
occurs as soon as the last stop bit has been output.
Caution After transmit data is written to TXS0, do not write the next transmit data before the
transmission completion interrupt signal (INTST0) is generated.
Figure 13-9. Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
TXD0 (output)
Start D0
D1
D2
D6 D7 Parity Stop
INTST0
2. Stop bit length: 2
TXD0 (output)
Start D0
D1
D2
D6
D7 Parity
Stop
INTST0
User’s Manual U18698EJ1V0UD
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