UPD78F0411GA-GAM-AX Datasheet, PDF (483/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage
(VDD)
VLVI
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Set LVI to be
used for reset
1.8 V^{Note 1}
VPOC = 1.59 V (TYP.)
0V
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
Operation
CPU _stops
Internal reset signal
0.5 V/ms (MIN.)^{Note 2}
Note 3
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Note 3
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Wait for voltage
stabilization
(1.93 to 5.39 ms)
Normal operation Reset period
(internal high-speed (oscillation
oscillation clock)^{Note 4} stop)
Normal operation Reset period Wait for voltage
(internal high-speed (oscillation stabilization
oscillation clock)^{Note 4} stop) (1.93 to 5.39 ms)
Normal operation
(internal high-speed
oscillation clock)^{Note 4}
Reset processing (11 to 47 μs)
Reset processing (11 to 47 μs)
Reset processing (11 to 47 μs)
Operation stops
Notes 1.
2.
3.
4.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.) on power application, input a low level
to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V
POC mode by using an option byte (POCMODE = 1).
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark VLVI: LVI detection voltage
VPOC: POC detection voltage
User’s Manual U18698EJ1V0UD
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