UPD78F0411GA-GAM-AX Datasheet, PDF (484/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Supply voltage
(VDD)
VLVI
VDDPOC = 2.7 V (TYP.)
1.8 V^{Note 1}
VPOC = 1.59 V (TYP.)
0V
Internal high-speed
oscillation clock (fRH)
High-speed
system clock (fXH)
(when X1 oscillation
is selected)
Operation
CPU
stops
Internal reset signal
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Set LVI to be
used for reset
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
Normal operation Reset period
(internal high-speed (oscillation
oscillation clock)^{Note 2} stop)
Normal operation
(internal high-speed
oscillation clock)^{Note 2}
Reset period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)^{Note 2}
Reset processing (11 to 47 μs)
Reset processing (11 to 47 μs)
Reset processing (11 to 47 μs)
Operation stops
Notes 1.
2.
The operation guaranteed range is 1.8 V ≤ VDD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
Remark VLVI: LVI detection voltage
VPOC: POC detection voltage
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User’s Manual U18698EJ1V0UD