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| UPD78F0411GA-GAM-AX Datasheet, PDF (538/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents | |||
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CHAPTER 26 INSTRUCTION SET
Instruction
Mnemonic
Group
Operands
Call/return CALL
!addr16
CALLF
!addr11
CALLT
[addr5]
BRK
RET
RETI
RETB
Stack
PUSH
manipulate
POP
MOVW
Unconditional BR
branch
Conditional BC
branch
BNC
BZ
BNZ
PSW
rp
PSW
rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Bytes
Clocks
Note 1 Note 2
Operation
Flag
Z AC CY
3
7
â (SP â 1) â (PC + 3)H, (SP â 2) â (PC + 3)L,
PC â addr16, SP â SP â 2
2
5
â (SP â 1) â (PC + 2)H, (SP â 2) â (PC + 2)L,
PC15 â 11 â 00001, PC10 â 0 â addr11,
SP â SP â 2
1
6
â (SP â 1) â (PC + 1)H, (SP â 2) â (PC + 1)L,
PCH â (00000000, addr5 + 1),
PCL â (00000000, addr5),
SP â SP â 2
1
6
â (SP â 1) â PSW, (SP â 2) â (PC + 1)H,
(SP â 3) â (PC + 1)L, PCH â (003FH),
PCL â (003EH), SP â SP â 3, IE â 0
1
6
â PCH â (SP + 1), PCL â (SP),
SP â SP + 2
1
6
â PCH â (SP + 1), PCL â (SP),
PSW â (SP + 2), SP â SP + 3
RRR
1
6
â PCH â (SP + 1), PCL â (SP),
PSW â (SP + 2), SP â SP + 3
RRR
1
2
â (SP â 1) â PSW, SP â SP â 1
1
4
â (SP â 1) â rpH, (SP â 2) â rpL,
SP â SP â 2
1
2
â PSW â (SP), SP â SP + 1
RRR
1
4
â rpH â (SP + 1), rpL â (SP),
SP â SP + 2
4
â
10 SP â word
2
â
8 SP â AX
2
â
8 AX â SP
3
6
â PC â addr16
2
6
â PC â PC + 2 + jdisp8
2
8
â PCH â A, PCL â X
2
6
â PC â PC + 2 + jdisp8 if CY = 1
2
6
â PC â PC + 2 + jdisp8 if CY = 0
2
6
â PC â PC + 2 + jdisp8 if Z = 1
2
6
â PC â PC + 2 + jdisp8 if Z = 0
Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
536
Userâs Manual U18698EJ1V0UD
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