UPD78F0411GA-GAM-AX Datasheet, PDF (211/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
<3> When the TM52 and CR52 (= FFH) values match, TM52 is cleared to 00, and the match signal causes TM000
to start counting up. Then, when the TM000 and CR000 values match, TM00 is cleared to 0000H, and a
match interrupt signal (INTTM000) is generated.
If input enable for the TI52 pin is controlled, external event count values within the input enable periods for the
TI52 pin can be measured, by reading TM52, the TM00 count value, and TMIF52 via interrupt servicing by the
TMH2 interrupt request signal (INTTMH2).
Figure 6-55. Operation Timing of External 24-bit Event Counter
TMH2 output signal
TI52
TI52 & TOH2
TM52
INTTM52
41H 42H 43H 00H 01H
FFH 00H 01H
FFH 00H 01H
FFH 00H 01H
FFH 00H 01H 02H 03H 04H 00H 01H
FFH 00H 01H
TM00
INTTMH2
1234H
0000H
0001H
0002H
FFFEH
FFFFH
0000H
0001H
Clear TM52/TM00 counter
Read TM52/TM00 count value
Clear TM52/TM00 counter
Read TM52/TM00 count value
User’s Manual U18698EJ1V0UD
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