UPD78F0411GA-GAM-AX Datasheet, PDF (474/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 20 RESET FUNCTION
Figure 20-2. Timing of Reset by RESET Input
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock Normal operation
RESET
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Reset period
(oscillation stop)
Reset
processing
(11 to 47 μs)
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Internal reset signal
Port pin
Delay
Delay
(5 μs (TYP.))
Hi-Z
Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow
Internal high-speed
oscillation clock
High-speed system clock
(when X1 oscillation is selected)
CPU clock
Watchdog timer
overflow
Normal operation
Wait for oscillation
accuracy stabilization
(86 to 361 μs)
Reset period
(oscillation stop)
Reset
processing
(11 to 47 μs)
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Internal reset signal
Port pin
Hi-Z
Caution A watchdog timer internal reset resets the watchdog timer.
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User’s Manual U18698EJ1V0UD