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UPD78F0411GA-GAM-AX Datasheet, PDF (331/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents
CHAPTER 13 SERIAL INTERFACE UART0
(e) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data
reception, a reception error interrupt (INTSR0) is generated.
Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception
error interrupt (INTSR0) servicing (see Figure 13-3).
The contents of ASIS0 are cleared to 0 when ASIS0 is read.
Reception Error
Parity error
Framing error
Overrun error
Table 13-3. Cause of Reception Error
Cause
The parity specified for transmission does not match the parity of the receive data.
Stop bit is not detected.
Reception of the next data is completed before data is read from receive buffer
register 0 (RXB0).
(f) Noise filter of receive data
The RXD0 signal is sampled using the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configured as shown in Figure 13-11, the internal processing of the reception operation
is delayed by two clocks from the external signal status.
Base clock
Figure 13-11. Noise Filter Circuit
RXD0
In
Q
Internal signal A
Match detector
In
Q
LD_EN
Internal signal B
User’s Manual U18698EJ1V0UD
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