UPD78F0411GA-GAM-AX Datasheet, PDF (446/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 17 INTERRUPT FUNCTIONS
(3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H,
and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory
manipulation instruction.
Reset signal generation sets these registers to FFH.
Figure 17-4. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H)
Address: FFE8H After reset: FFH R/W
Symbol
<7>
6
5
PR0L
SREPR6
1
1
<4>
PPR3
<3>
PPR2
<2>
PPR1
<1>
PPR0
<0>
LVIPR
Address: FFE9H After reset: FFH R/W
Symbol
<7>
<6>
<5>
PR0H
TMPR010 TMPR000 TMPR50
<4>
TMPRH0
<3>
TMPRH1
<2>
STPR0
<1>
STPR6
<0>
SRPR6
Address: FFEAH After reset: FFH R/W
Symbol
<7>
6
<5>
PR1L
TMPR52
1
RTCPR
<4>
KRPR
<3>
TMPR51
<2>
RTCIPR
<1>
SRPR0
<0>
ADPR^Note
Address: FFEBH After reset: FFH R/W
Symbol
7
6
5
4
3
2
<1>
<0>
PR1H
1
1
1
1
1
1
MCGPR TMHPR2
XXPRX
0
1
High priority level
Low priority level
Priority level selection
Note μPD78F041x only.
Caution Be sure to set bits 5 and 6 of PR0L, bit 6 of PR1L, and bits 2 to 7 of PR1H to 1.
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User’s Manual U18698EJ1V0UD