UPD78F0411GA-GAM-AX Datasheet, PDF (143/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 5 CLOCK GENERATOR
Table 5-8. Maximum Time Required for Main System Clock Switchover
Set Value Before Switchover
MCM0
0
1
0
1 + 2fXH/fRH clock
Set Value After Switchover
MCM0
1
1 + 2fRH/fXH clock
Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2
(XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a
reset release.
Remarks 1. The number of clocks listed in Table 5-8 is the number of main system clocks before switchover.
2. Calculate the number of clocks in Table 5-8 by removing the decimal portion.
Example When switching the main system clock from the internal high-speed oscillation clock to the
high-speed system clock (@ oscillation with fRH = 8 MHz, fXH = 10 MHz)
1 + 2fRH/fXH = 1 + 2 × 8/10 = 1 + 2 × 0.8 = 1 + 1.6 = 2.6 → 2 clocks
5.6.9 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-9. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock
Internal high-speed
oscillation clock
X1 clock
External main system clock
XT1 clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
Flag Settings of SFR
Register
RSTOP = 1
MSTOP = 1
OSCSELS = 0
User’s Manual U18698EJ1V0UD
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