UPD78F0411GA-GAM-AX Datasheet, PDF (493/564 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

CHAPTER 22 LOW-VOLTAGE DETECTOR
Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Supply Voltage (VDD)) (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage (VDD)
VLVI
VPOC = 1.59 V (TYP.)
LVIMK flag
(set by software) ^{HNote 1}
<1>
LVISEL flag
<3>
(set by software) _L
LVION flag
(set by software)
LVIF flag
LVIMD flag
(set by software)
<2>
<4>
Not cleared
<5> Wait time
<6>
Note 2
<7>
Not cleared
LVIRF flag^{Note 3}
Not cleared
Not cleared
Clear
Clear
Clear
Time
LVI reset signal
POC reset signal
Cleared by
software
Cleared by
software
Internal reset signal
Notes 1.
2.
3.
The LVIMK flag is set to “1” by reset signal generation.
The LVIF flag may be set (1).
LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark <1> to <7> in Figure 22-5 above correspond to <1> to <7> in the description of “When starting
operation” in 22.4.1 (1) When detecting level of supply voltage (VDD).
User’s Manual U18698EJ1V0UD
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