PIC32MX440F256H-80I Datasheet, PDF (99/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 6-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER (CONTINUED)
bit 6
BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one Wait state for address setup
0 = Data RAM accesses from CPU have zero Wait states for address setup
bit 5-3
Reserved: Write ‘0’; ignore read
bit 2-0
BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111...011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
001 = Arbitration Mode 1
000 = Arbitration Mode 0
Note: For detailed descriptions of the arbitration modes, refer to the ‘PIC32MX Family Reference Manual,
Chapter 3. Memory Organization, Section 3.5 Bus Matrix’ (DS61132).
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 97