PIC32MX440F256H-80I Datasheet, PDF (354/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 14-6:
32-BIT GATED CLOCK
COUNTER/TIMER
INITIALIZATION
T4CON = 0x0;
//Stop Timer4 and clear
T5CON = 0x0;
//Stop Timer5 and clear
T4CONSET = 0x00C8; //32-bit mode,
//gate enable,
//internal clock,
//1:16 prescale
TMR4 = 0x0;
//Clear TMR4 and TMR5
//Same as TMR4 = 0x0
PR4 = 0xFFFFFFFF; //Load PR4 and PR5 regs
//Same as PR4 =0xFFFFFFFF
T4CONSET = 0x8000; //Start 32-bit timer
14.3.9 TIMER CLOCK PRESCALER
Timer clock prescale bits, TCKPS<1:0>
(TxCON<6:4>), are used to divide the timer clock
source permitting the TMR register to increment on
every 1, 2, 4, 8, 16, 32, 64, or 256 (PBCLK or external)
clock cycles. For example, if the clock prescale is 1:8,
then the timer increments on every 8th timer clock
cycle.
14.3.10 CONSIDERATIONS
Associated with the clock prescale selection bits is a
prescale counter. The timer prescale counter is cleared
when any of the following conditions occur:
1. Any device Reset, except a Power-on Reset.
2. The timer is disabled.
3. Any write to the TMR register.
Note:
When the timer clock source is external and
the timer clock prescale = N (other than
1:1), 2 to 3 external clock cycles are
required to reset and synchronize the
prescaler.
• When the timer clock source is external and the
timer clock prescale = N (other than 1:1), 2 to 3
external clock cycles are required, after the timer
ON bit is set = 1, before the TMRx Count register
increments.
• After a timer match event (TMRx = PRx) and
depending on the timer clock prescale setting N
(other than 1:1), the timer will require N additional
(PBCLK or external) clock cycles before the
TMRx Counter register resets to 0x0000. Reading
the TMRx Count register just after the timer match
event, but before the TMRx Count register is
reset, will return the timer match value.
DS61143E-page 352
Preliminary
© 2008 Microchip Technology Inc.