PIC32MX440F256H-80I Datasheet, PDF (389/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 17-1: SPIXCON: SPI CONTROL REGISTER
R/W-0
R/W-0
R/W-0
r-x
r-x
r-x
r-x
r-x
FRMEN FRMSYNC FRMPOL
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
R/W-0
r-x
—
—
—
—
—
SPIFE
—
bit 16
R/W-0
ON
bit 15
R/W-0
FRZ
R/W-0
SIDL
R/W-0
DISSDO
R/W-0
MODE32
R/W-0
MODE16
R/W-0
SMP
R/W-0
CKE
bit 8
R/W-0
R/W-0
R/W-0
r-x
r-x
r-x
r-x
r-x
SSEN
CKP
MSTEN
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31
bit 30
bit 29
bit 28-18
bit 17
bit 16
bit 15
bit 14
bit 13
bit 12
FRMEN: Framed SPI Support bit
1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
FRMPOL: Frame Sync Polarity bit (Framed SPI mode only)
1 = Frame pulse is active-high
0 = Frame pulse is active-low
Reserved: Write ‘0’; ignore read
SPIFE: Frame Sync Pulse Edge Select bit (framed SPI mode only)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock
Reserved: Write ‘0’; ignore read
ON: SPI Peripheral On bit
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
FRZ: Freeze in DEBUG Exception Mode bit
1 = Freeze operation when CPU enters Debug Exception mode
0 = Continue operation when CPU enters Debug Exception mode
Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in Normal mode.
SIDL: Stop in IDLE Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register
0 = SDOx pin is controlled by the module
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 387