PIC32MX440F256H-80I Datasheet, PDF (467/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
20.5 I/O Pin Control
TABLE 20-11: REQUIRED I/O PIN RESOURCES FOR MASTER MODES
I/O Pin
Name
PMPCS2 / PMA15
PMPCS1 / PMA14
PMA<13:2>
PMA1 / PMALH
PMA0 / PMALL
De-
multiplex
Yes⁽²⁾
Yes⁽²⁾
Yes⁽²⁾
No⁽¹⁾
No⁽¹⁾
Partial
Multiplex
Yes⁽²⁾
Yes⁽²⁾
Yes⁽³⁾
No⁽¹⁾
Yes⁽²⁾
Full
Multiplex
Yes⁽²⁾
Yes⁽²⁾
No⁽¹⁾
Yes⁽⁴⁾
Yes⁽⁴⁾
Functional Description
PMP Chip Select 2 / Address A15
PMP Chip Select 1 / Address A14
PMP Address A13..A2
PMP Address A1 / Address Latch High
PMP Address A0 / Address Latch Low
PMRD / PMWR
Yes
Yes
Yes
PMP Read / Write Control
PMWR / PMENB
PMD<15:0>
Yes
Yes⁽⁵⁾
Yes
Yes⁽⁵⁾
Yes
Yes⁽⁵⁾
PMP Write / Enable Control
PMP Bidirectional Data Bus D15..D0
Note: 1. “No” indicates the pin is not required and is available as a general purpose I/O pin when the corresponding
PMAEN bit is cleared, = 0.
2. Depending on the application, not all PMA<15:0> or CS2, CS1 may be required.
3. When Partial Multiplex mode is selected (ADDRMUX<1:0> = 01), the lower 8 Address lines are multiplexed
with PMD<7:0>, PMA<0> becomes (PMALL) and PMA<7:1> are available as general purpose I/O pins.
4. When Full Multiplex mode is selected (ADDRMUX<1:0> = 10 or 11), all 16 Address lines are multiplexed with
PMD<15:0>, PMA<0> becomes (PMALL), PMA<1> becomes (PMALH) and PMA<13:2> are available as
general purpose I/O pins.
5. If MODE16 = 0, then only PMD<7:0> are required. PMD<15:8> are available as general purpose
I/O pins.
6. Data pins PMD<15:0> are available on 100-pin PIC32MX3XX/4XX devices and larger. For all other device
variants, only pins PMD<7:0> are available.
When enabling any of the PMP module for Slave mode
operations, the PMPCS1, PMRD, PMWR control pins,
PMD<7:0> data pins and PMA<1:0> address pins are
automatically enabled and configured. The user is how-
ever responsible for selecting the appropriate polarity
for these control lines.
TABLE 20-12: REQUIRED I/O PIN RESOURCES FOR SLAVE MODES
I/O Pin Name
Legacy
Buffered Addressable
Functional Description
PMPCS1 / PMA14
PMA1 / PMALH
PMA0 / PMALL
Yes
No⁽¹⁾
No⁽¹⁾
Yes
No⁽¹⁾
No⁽¹⁾
Yes
Chip Select
Yes
Address A1
Yes
Address A0
PMRD / PMWR
Yes
Yes
Yes
Read Control
PMWR / PMENB
PMD<7:0>
Yes
Yes⁽²⁾
Yes
Yes⁽²⁾
Yes
Yes⁽²⁾
Write Control
Bidirectional Data Bus D7..D0
Note: 1. “No” indicates the pin is not required and is available as a general purpose I/O pin when the corresponding
PMAEN bit is cleared, = 0.
2. Slave modes use PMD<7:0> only. Pins PMD<15:8> are available as general purpose I/O pins. Control bit
MODE16 (PMMODE<10>) is ignored.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 465