PIC32MX440F256H-80I Datasheet, PDF (75/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

4.2.1.4
System Clock Phase Locked Loop
(PLL)
The system clock PLL provides a user configurable
input divider, multiplier, and output divider which can be
used with the XT, HS and EC Primary Oscillator modes
and with the Internal Fast RC Oscillator (FRC) mode to
create a variety of clock frequencies from a single clock
source.
The Input divider, multiplier, and output divider control
initial value bits are contained in the in the DEVCFG2
device Configuration register. The multiplier and output
divider bits are also contained in the OSCCON register.
As part of a device Reset, values from the device con-
figuration register, DEVCFG2, are copied to the
OSCCON register. This allows the user to preset the
input divider to provide the appropriate input frequency
to the PLL and set an initial PLL multiplier when pro-
gramming the device. At runtime the multiplier, divider
and output divider can be changed by software to scale
the clock frequency to suit the application. The PLL
input divider cannot be changed at run time. This is to
prevent applying an input frequency outside the speci-
fied limits to the PLL.
To configure the PLL the following steps are required:
1. Calculate the PLL input divider, PLL multiplier,
and PLL output divider values.
2. Set the PLL input divider and the initial PLL mul-
tiplier value in the DEVCFG2 register when pro-
gramming the part.
3. At runtime the PLL multiplier and PLL output
divider can be changed to suit the application.
Combinations of PLL input divider, multiplier and output
divider provide a combined multiplier of approximately
0.006 to 24 times the input frequency. For reliable oper-
ation the output of the PLL module must not exceed the
maximum clock frequency of the device. The PLL input
divider value should be chosen to limit the input fre-
quency to the PLL to the range of 4 MHz to 5 MHz.
Due to the time required for the PLL to provide a stable
output, a Status bit LOCK (OSCCON<5>) is provided.
When the clock input to the PLL is changed, this bit is
driven low (‘0’). After the PLL has achieved a lock or the
PLL start-up timer has expired, the bit is set. The bit will
be set upon the expiration of the timer even if the PLL
has not achieved a lock.
PIC32MX3XX/4XX
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 73