PIC32MX440F256H-80I Datasheet, PDF (216/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 10-8:
r-x
—
bit 31
DCHXECON: DMA CHANNEL X EVENT CONTROL REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
r-x
—
bit 24
R/W-1
bit 23
R/W-1
R/W-1
R/W-1
R/W-1
CHAIRQ<7:0>
R/W-1
R/W-1
R/W-1
bit 16
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
CHSIRQ<7:0>
R/W-1
R/W-1
R/W-1
bit 8
S-0
S-0
R/W-0
R/W-0
R/W-0
r-x
r-x
r-x
CFORCE
CABORT
PATEN
SIRQEN AIRQEN
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-24
bit 23-16
bit 15-8
bit 7
bit 6
bit 5
bit 4
Reserved: Write ‘0’; ignore read
CHAIRQ<7:0>: IRQ that will abort Channel Transfer bits
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•••
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
CHSIRQ<7:0>: IRQ that will Start Channel Transfer bits
11111111 = Interrupt 255 will initiate a DMA transfer
•••
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
DS61143E-page 214
Preliminary
© 2008 Microchip Technology Inc.