PIC32MX440F256H-80I Datasheet, PDF (585/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
FIGURE 28-3:
OVERVIEW OF PIC32MX3XX/4XX-BASED JTAG COMPLIANT APPLICATION
SHOWING DAISY-CHAINING OF COMPONENTS
PIC32MX Device-Based Application
PIC32MX
PIC32MX
(or other
JTAG compliant
device)
JTAG
Controller
TDI
TDO
TCK
TMS
JTAG Connector
Note: Power and ground connections not shown.
In PIC32MX3XX/4XX devices, the hardware for the
JTAG boundary scan is implemented as a peripheral
module (i.e., outside of the CPU core) with additional
integrated logic in all I/O ports. A logical block diagram
of the JTAG module is shown in Figure 28-1. It consists
of the following key elements:
• TAP Interface Pins (TDI, TMS, TCK and TDO)
• TAP Controller
• Instruction Shift register and Instruction Register
(IR)
• Data Registers (DR)
28.2.4.1 Test Access Port (TAP) and TAP
Controller
The Test Access Port (TAP) on the PIC32MX3XX/4XX
device is a general purpose port that provides test
access to many built-in support functions and test logic
defined in IEEE 1149.1. The TAP is enabled by the
JTAGEN bit in the DDPCON register. The TAP is
enabled, JTAGEN = 1, by default when the device exits
Power-on-Reset (POR) or any device Reset. Once
enabled, the designated I/O pins become dedicated
TAP pins.
The PIC32MX3XX/4XX implements a 4-pin JTAG
interface with these pins:
• TCK (Test Clock Input): Provides the clock for test
logic.
• TMS (Test Mode Select Input): Used by the TAP
to control test operations.
• TDI (Test Data Input): Serial input for test
instructions and data.
• TDO (Test Data Output): Serial output for test
instructions and data.
28.2.4.2 JTAG Registers
The JTAG module uses a number of registers of vari-
ous sizes as part of its operation. In terms of bit count,
most of the JTAG registers are single bit register cells,
integrated into the I/O ports. Regardless of their loca-
tion within the module, none of the JTAG registers are
located within the device data memory space, and
cannot be directly accessed by the user in normal
operating modes.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 583