PIC32MX440F256H-80I Datasheet, PDF (465/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 20-6: ADDRESSABLE PARALLEL SLAVE PORT INITIALIZATION
IEC1CLR = 0x0004
//Disable PMP int
PMCON = 0x0000
//Stop and Configure
PMMODE = 0x0100
//Config PMMODE
IPC7SET = 0x001C;
//Priority level=7
IPC7SET = 0x0003;
//subpriority=3
//Same as...
//IPC7SET=0x001F
IFS1CLR = 0x0004;
//Clear PMP int flag
IEC1SET = 0x0004;
//Enable PMP int
PMCONSET = 0x8000;
//Enable PMP module
20.4 PMP Interrupts
The PMP module has the ability to generate the follow-
ing types of interrupts reflecting the events that occur
during data transfers.
Master mode:
• Interrupt on every read and write operation.
Legacy Slave mode:
• Interrupt on every read and write byte
Buffered Slave mode:
• Interrupt on every read and write byte
• Interrupt on read or write byte of Buffer 3
(PMDOUT<31:24>)
Addressable Slave mode:
• Interrupt on every read and write byte
• Interrupt on read or write byte of Buffer 3
(PMDOUT<31:24>), PMA<1:0> = 11
The PMP module is enabled as a source of interrupt
using the PMP interrupt enable bit:
• PMPIE (IEC1<2>).
The interrupt priority level and subpriority level bits
must also be configured:
- PMPIP<2:0> (IPC7<4:2>)
- PMPIS<1:0> (IPC7<1:0>)
• The PMP interrupt status flag, PMPIF (IFS1<2>)
is typically cleared by the user’s software in the
ISR.
Below is a partial code example of an ISR.
Note:
It is the user’s responsibility to clear the
corresponding interrupt flag bit before
returning from an ISR.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 463