PIC32MX440F256H-80I Datasheet, PDF (233/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
EXAMPLE 10-2: CONFIGURING THE DMA FOR PATTERN MATCH OPERATION
/*
The following code example illustrates the DMA channel 0 configuration for data transfer with
pattern match enabled. Transfer from the UART1 a <CR> ended string, at most 256 characters long
*/
IEC1CLR=0x00010000;
IFS1CLR=0x00010000;
// disable DMA channel 0 interrupts
// clear any existing DMA channel 0 interrupt flag
DMACONSET=0x00008000;
DCH0CON=0x03;
// enable the DMA controller
// channel off, priority 3, no chaining
DCH0ECON=(27 <<8)| 0x30;
DCH0DAT=’\r’;
// start irq is UART1 RX, pattern match enabled
// pattern value, carriage return
DCH0SSA=VirtToPhys(&U1RXREG);
DCH0DSA=0x1d020000;
DCH0SSIZ=1;
DCH0DSIZ=0;
DCH0CSIZ=1;
// program the transfer
// transfer source physical address
// transfer destination physical address
// source size is 1 byte
// dst size at most 256 bytes
// one byte per UART transfer request
DCH0INTCLR=0x00ff00ff;
DCH0INTSET=0x00090000;
// clear existing events, disable all interrupts
// enable Block Complete and error interrupts
IPC9CLR=0x0000001f;
IPC9SET=0x00000016;
IEC1SET=0x00010000;
// clear the DMA channel 0 priority and subpriority
// set IPL 5, subpriority 2
// enable DMA channel 0 interrupt
DCH0CONSET=0x80;
// turn channel on
// wait for an UART RX interrupt to initiate a transfer
// do something else
// will get an interrupt when the transfer is done
// or when an address error occurred
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 231