PIC32MX440F256H-80I Datasheet, PDF (459/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

20.3.4 WRITE OPERATION
To perform a write onto the parallel port, the user
writes to the PMDIN register (same register used for a
read operation). This causes the module to first acti-
vate the Chip Select lines and the address bus. The
write data from the PMDIN register is placed onto the
PMD data bus and the write line PMPWR is strobed.
20.3.5 PARALLEL MASTER PORT STATUS
In addition to the PMP interrupt, a BUSY bit is
provided to indicate the status of the module. This bit
is only used in Master modes.
While any read or write operation is in progress, the
BUSY bit is set for all but the very last peripheral bus
cycle of the operation. While the bit is set, any request
by the user to initiate a new operation will be ignored
(i.e., writing or reading the PMDIN register will not initi-
ate either a read nor a write).
EXAMPLE 20-2: POLLING THE BUSY FLAG
/*An generic C example PMP write function
utilizing the BUSY bit.
*/
pmpWrite(unsigned int value)
{
while(PMMODE & 0x8000); // PMP busy?
PMDIN = value; // perform write
}
/*An MPLAB C32 example PMP write function
utilizing BUSY bit.
*/
pmpWrite(unsigned int value)
{
while(PMMODEbits.BUSY); // PMP busy?
PMDIN = value; // perform write
}
In most applications, the PMP’s Chip Select pin(s) pro-
vide the Chip Select interface and are under the timing
control of the PMP module. However, some applica-
tions may require the PMP Chip Select pin(s) not be
configured as a Chip Select, but as a high-order
address line, such as PMA<14> or PMA<15>. In this
situation, the application’s Chip Select function must be
provided by an available I/O port pin under software
control. In these cases, it is especially important that
the user’s software poll the BUSY bit to ensure any
read or write operation is complete before de-asserting
the software controlled Chip Select.
The following example illustrates a common technique.
PIC32MX3XX/4XX
If a large number of wait-states are used, or if the
PBCLK clock is operating slower than the SYSCLK
clock, it is possible for the PMP module to be in the pro-
cess of completing a read or write operation when the
next CPU instruction is attempting to read or write the
PMP module. For this reason, it is highly recommended
that the PMP’s BUSY bit be checked prior to any read
or write operation and any user operation that modifies
the PMADDR address register. See the following code
example.
Note:
During any Master mode read or write
operation, the busy flag will always de-
assert 1 peripheral bus clock cycle
(T_PBCLK), before the end of the operation,
including Wait states.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 457