PIC32MX440F256H-80I Datasheet, PDF (79/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

4.2.1.7.1 Enabling the LPRC Oscillator
Since it serves the PWRT clock source, the LPRC
oscillator is disabled at Power-on Reset whenever the
on-board voltage regulator is enabled. After the PWRT
expires, the LPRC oscillator will remain on if any one of
the following is true:
• The Fail-Safe Clock Monitor is enabled.
• The WDT is enabled.
• The LPRC oscillator is selected as the system
clock (COSC2:COSC0 = 100).
If none of the above is true, the LPRC will shut off after
the PWRT expires.
4.2.2
PERIPHERAL BUS CLOCK (PBCLK)
GENERATION
The PBCLK is derived from the System Clock (SYS-
CLK) divided by PBDIV<1:0> (OSCCON<20:19>). The
PBCLK Divisor bits PBDIV<1:0> allow postscalers of
1:1, 1:2, 1:4, and 1:8. Refer to the individual peripheral
module section(s) for information regarding which bus
a specific peripheral uses.
Notes:
When the PBDIV divisor is set to a ratio of
‘1:1’ the SYSCLK and PBCLK are equiva-
lent in frequency. The PBCLK frequency is
never greater than the processor clock fre-
quency.
The effect of changing the PBCLK fre-
quency on individual peripherals should be
taken into account when selecting or
changing the PBDIV value.
Performing back-to-back operations on
PBCLK peripheral registers when the PB
divisor is not set at 1:1 will cause the CPU
to stall for a number of cycles. This stall
occurs to prevent an operation from occur-
ring before the pervious one has com-
pleted. The length of the stall is
determined by the ratio of the CPU and
PBCLK and synchronizing time between
the two busses.
Changing the PBCLK frequency has no
effect on the SYSCLK peripherals
operation.
PIC32MX3XX/4XX
4.2.3
USB Clock (USBCLK)
Generation
The USBCLK can be derived from 8 MHz internal FRC
oscillator, 48 MHz POSC, or 96 MHz PLL from POSC.
For normal operation, the USB module requires exact
48 MHz clock. When using 96 MHz PLL, the output is
internally divided to obtain 48 MHz clock. The FRC
clock source is used to detect USB activity and bring
USB module out of SUSPEND mode. Once USB mod-
ule is out of SUSPEND mode, it starts using any of two
48 MHz clock sources. The internal FRC oscillator is
not used for normal USB module operation.
4.2.3.0.1 USB Clock Phase Locked Loop (UPLL)
The USB clock PLL provides a user configurable input
divider which can be used with the XT, HS and EC pri-
mary oscillator modes and with the Internal Fast RC
Oscillator (FRC) mode to create a variety of clock fre-
quencies from a clock source. The actual source must
be able to provide stable clock as required by the USB
specifications.
The UPLL enable and Input divider bits are contained
in the in the DEVCFG2 device configuration register.
The input to the UPLL must be limited to 4 MHz only.
Appropriate input divider must be selected to ensure
that the UPLL input is 4 MHz.
To configure the UPLL the following steps are required:
1. Enable USB PLL by setting FUPLLEN bit in
DEVCFG2 register.
2. Based on the source clock, calculate the UPLL
input divider value such that the PLL input is 4
MHz
3. Set the UPLL input divider FUPLLIDIV bits in the
DEVCFG2 register when programming the part.
4.2.3.0.2 USB PLL Lock Status
The ULOCK bit (OSCCON<6>) is a read-only status bit
that indicates the lock status of the USB PLL. It is auto-
matically set after the typical time delay for the PLL to
achieve lock, also designated as T_ULOCK. If the PLL
does not stabilize properly during start-up, ULOCK may
not reflect the actual status of PLL lock, nor does it
detect when the PLL loses lock during normal opera-
tion.
The ULOCK bit is cleared at a Power-on Reset. It
remains clear when any clock source not using the PLL
is selected.
Refer to the Electrical Characteristics section in the
specific device data sheet for further information on the
USB PLL lock interval.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 77