PIC32MX440F256H-80I Datasheet, PDF (284/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
11.5.3.1 Buffer Descriptor Format
The buffer descriptor is used in the following formats:
• Control
• Status.
Buffer descriptor control format, in which software
writes the descriptor and hands it to hardware, is
shown in Figure 11-3.
Buffer descriptor status format, in which hardware
writes the descriptor and hands it back to software, is
shown in Figure 11-4.
FIGURE 11-3:
USB BUFFER DESCRIPTOR FORMAT: SOFTWARE → HARDWARE
Address Offset +0
31
26 25
16 15
—
BYTE COUNT<9:0>
—
876543210
—
Address Offset +4
31
0
BUFFER ADDRESS<31:0>
Address Offset +0
bit 25-16 BYTE_COUNT<9:0>: Byte Count bits
Byte count represents the number of bytes to be transmitted or the maximum number of bytes to be
received during a transfer.
bit 7
UOWN: USB Own bit
1 = USB module owns the BD and its corresponding buffer
CPU must not modify the BD or the buffer.
0 = CPU owns the BD and its corresponding buffer
USB module ignores all other fields in the BD.
USBFRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode.
Note: This bit can be programmed by either the CPU or the USB module, and it must be initialized by the
user to the desired value prior to enabling the USB module.
bit 6
DATA0/1: Data Toggle Packet bit
1 = Transmit a Data 1 packet or Check received PID = DATA1, if DTS = 1
0 = Transmit a Data 0 packet or Check received PID = DATA1, if DTS = 1
bit 5
KEEP: BD Keep Enable bit
1 = USB will keep the BD indefinitely once UOWN is set
U1STAT FIFO will not be updated and TRNIF bit will not be set at the end of each transaction.
0 = USB will hand back the BD once a token has been processed
bit 4
NINC: DMA Address Increment Disable bit
1 = DMA address increment disabled
0 = DMA address increment enabled
bit 3
DTS: Data Toggle Synchronization Enable bit
1 = Data Toggle Synchronization is enabled – data packets with incorrect sync value will be ignored
0 = No Data Toggle Synchronization is performed
Note: Expected value of DATA PID (DATA0/DATA1) specified in the DATA0/1 field.
DS61143E-page 282
Preliminary
© 2008 Microchip Technology Inc.