PIC32MX440F256H-80I Datasheet, PDF (191/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 9-9: CHELRU: CACHE LRU REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
R-0
—
—
—
—
—
—
—
CHELRU<24>
bit 31
bit 24
R-0
bit 23
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHELRU<23-16>
bit 16
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHELRU<15-8>
bit 8
R-0
bit 7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
CHELRU<7-0>
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-25
bit 24-0
Reserved: Write ‘0’; ignore read
CHELRU<24:0>: Cache Least Recently Used State Encoding bits
CHELRU indicates the Pseudo-LRU state of the cache.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 189