PIC32MX440F256H-80I Datasheet, PDF (90/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
5.2 Reset Modes
The PIC32MX3XX/4XX internal device Reset signal is
SYSRST and can be generated from multiple Reset
sources, such as POR (Power-on Reset), BOR
(Brown-out Reset), MCLR (Master Clear Reset),
WDTO (Watchdog Time-out Reset), SWR (Software
Reset) and CMR (Configuration Mismatch Reset). A
Reset source sets a corresponding status bit in the
RCON register to indicate the type of Reset (see
Register 5-1). A system Reset is active at first the POR
and asserted until device configuration settings are
loaded and the clock oscillator sources become stable.
The system Reset is then deasserted allowing the CPU
to start fetching code after 8 system clock cycles (SYS-
CLK).
5.2.1 POWER-ON RESET (POR)
A power-on event generates an internal Power-On
Reset pulse when a VDD rise is detected above VPOR.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate require-
ments to generate the POR pulse. In particular, VDD
must fall below VPOR before a new POR is initiated. For
more information on the VPOR and VDD rise rate speci-
fications, refer to Section 30.0 “Electrical Character-
istics” of this device family data sheet.
5.2.2 MCLR RESET (EXTR)
Whenever the MCLR pin is driven low, the device asyn-
chronously asserts SYSRST provided the input pulse on
MCLR is longer than a certain minimum width, as spec-
ified in Section 30.0 “Electrical Characteristics” of
this device family data sheet.
MCLR provides a filter to minimize the effects of noise
and to avoid unwanted Reset conditions. The EXTR bit
(RCON<7>) is set to indicate the MCLR Reset.
5.2.3 SOFTWARE RESET (SWR)
The PIC32MX3XX/4XX CPU core doesn’t provide a
specific RESET “instruction”; however, a hardware
Reset can be performed in software (Software Reset)
by executing a Software Reset command sequence:
• Write the system unlock sequence
• Set bit, SWRST (RSWRST<0>) = 1
• Read RSWRST register – Reset occurs
• Follow with “while(1);” or 4 “NOP” instructions
Writing a ‘1’ to the RSWRST register sets bit SWRST,
arming the Software Reset. The subsequent read of
the RSWRST register triggers the Software Reset,
which should occur on the next clock cycle following
the read operation. To ensure no other user code is
executed before the Reset event occurs, it is recom-
mended that 4 ‘NOP’ instructions or a “while(1);” state-
ment be placed after the READ instruction.
The SWR Status bit (RCON<6>) is set to indicate the
Software Reset.
EXAMPLE 5-1: SOFTWARE RESET COMMAND SEQUENCE
/* The following code illustrates a software Reset */
// assume interrupts are disabled
// assume the DMA controller is suspended
// assume the device is locked
/* perform a system unlock sequence */
// starting critical sequence
SYSKEY = 0x12345678; //write invalid key to force lock
SYSKEY = 0xAA996655 //write key1 to SYSKEY
SYSKEY = 0x556699AA //write key2 to SYSKEY
// OSCCON is now unlocked
/* set SWRST bit to arm reset */
RSWRSTSET = 1;
/* read RSWRST register to trigger reset */
unsigned int dummy;
dummy = RSWRST;
/* prevent any unwanted code execution until reset occurs*/
DS61143E-page 88
Preliminary
© 2008 Microchip Technology Inc.