PIC32MX440F256H-80I Datasheet, PDF (446/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 20-2: PMMODE: PARALLEL PORT MODE REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 23
bit 16
R-0
BUSY
bit 15
R/W-0
R/W-0
IRQM<1:0>
R/W-0
R/W-0
INCM<1:0>
R/W-0
MODE16
R/W-0
R/W-0
MODE<1:0>
bit 8
R/W-0
R/W-0
WAITB1<1:0>⁽¹⁾
bit 7
R/W-0
R/W-0
R/W-0
WAITM<3:0>
R/W-0
R/W-0
R/W-0
WAITE1<1:0>⁽¹⁾
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-16
Reserved: Write ‘0’; ignore read
bit 15
BUSY: Busy bit (Master modes only)
1 = Port is busy
0 = Port is not busy
bit 14-13
IRQM<1:0>: Interrupt Request Mode bits
11 = Reserved – do not use
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only)
01 = Interrupt generated at the end of the read/write cycle
00 = No Interrupt generated
bit 12-11
INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (MODE<1:0> = 00 only)
10 = Decrement ADDR<15:0> by 1 every read/write cycle^(2,5)
01 = Increment ADDR<15:0> by 1 every read/write cycle^(2,5)
00 = No increment or decrement of address
bit 10
MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer⁽⁴⁾
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
Note 1: Whenever WAITM3:WAITM0 = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: When ADDR15 and ADDR14 are used as CS2 and CS1, or ADDR15 is used as CS2, these bits are not
subject to auto-increment/decrement.
3: In Master Mode 1 or Master Mode 2, data pins PMD<15:0> are active when MODE16 = 1; data pins
PMD<7:0> are active when MODE16 = 0.
4: On 64-pin devices, data pins PMD<15:8> are not available.
5: The PMADDR register is always incremented/decremented by 1, regardless of the transfer data width.
DS61143E-page 444
Preliminary
© 2008 Microchip Technology Inc.