PIC32MX440F256H-80I Datasheet, PDF (229/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

10.2 DMA Controller Operation
A DMA channel will transfer data from a source to a
destination without CPU intervention.
DMA controller configuration resources:
• The DMA Controller and the corresponding DMA
channel have to be enabled using the ON
(DMACON<15>) and the CHEN (DCHxCON<7>)
bits.
• The source and destination of the transfer are
programmable using the DCHxSSA and
DCHxDSA registers respectively.
• The source and destination are further indepen-
dently configurable using the DCHxSSIZ and
DCHxDSIZ registers.
• A DMA transfer can be initiated in one of two
ways:
- Software can initiate a transfer by setting the
channel CFORCE (DCHxECON<7>) bit.
- An interrupt event occurs that matches the
CHSIRQ (DCHxECON<15:8>) interrupt and
SIRQEN = 1 (DCHxECON<4>). The user can
select any interrupt on the device to start a
DMA transfer.
Note:
BMX arbitration mode 2 (rotating priority) is
recommended when a system may
experience heavy bus load.
• At each event requiring a DMA transfer, a num-
ber of bytes specified by the cell size (DCHxCSIZ)
will be transferred (one or more transactions will
occur).
• The channel keeps track of the number of bytes
transferred from the source to destination, using
Source and Destination Pointers (DCHxSPTR
and DCHxDPTR).
• The Source and Destination Pointers are read-
only and are updated after every transaction.
• Interrupts are generated when the Source or
Destination pointer is half of the source or desti-
nation size (DCHxSSIZ/2 or DCHxDSIZ/2), or
when the source or destination counter equals the
size of the source or destination. These interrupts
are CHSHIF, CHDHIF and CHSDIF, CHDDIF,
respectively.
PIC32MX3XX/4XX
• The Source and Destination Pointers are reset:
- On any device Reset.
- When the DMA is turned off (ON bit
(DMACON<15>) is ‘0’).
Note:
Always wait for the channels to complete
the current transactions (or abort first and
make sure the transfers were successfully
aborted) before switching the DMA
controller OFF.
- A block transfer completes (regardless of the
state of CHAEN (DCHxCON<4>)).
- A pattern match terminates a transfer
(regardless of the state of auto-enable
CHAEN (DCHxCON<4>)).
- CABORT (DCHxECON<6>) flag is written.
Note:
If the DMA channel is suspended in the mid-
dle of a transfer (If CHEN (DCHxCON)<7>
= 0) or if the DMA controller is suspended in
the middle of a transfer (If SUSPEND
(DMACON)<12> = 1) and a CABORT is
issued, the Source, Destination and Cell
pointers are not Reset.
- If the channel source address (DCHxSSA) is
updated, the Source Pointer (DCHxSPTR)
will be reset.
- Similarly, updates to the Destination Address
(DCHxDSA) will cause the Destination
Pointer (DCHxDPTR) to be reset.
• Normally, the DMA channel remains enabled until
the DMA channel has completed a block transfer
unless the auto-enable feature is turned on
(i.e., CHAEN = 1).
• When the channel is disabled, further transfers
will be prohibited until the channel is re-enabled
(CHEN is set to ‘1’).
• A DMA transfer request will be stopped/aborted
by:
- Writing the CABORT bit (DCHxECON<6>).
- Pattern match occurs if pattern match is
enabled PATEN = 1 (DCHxECON<5>), pro-
vided that channel CHAEN is not set.
- Interrupt event occurs on the device that
matches the CHAIRQ (DCHxECON<23:16>)
interrupt if enabled by AIRQEN
(DCHxECON<3>).
- An address error is detected.
- A block transfer completes provided that
Channel Auto-Enable mode (CHAEN) is not
set.
• When a channel abort interrupt occurs, the
Channel Abort Interrupt Flag, CHTAIF,
(DCHxINT<1>) is set. This allows the user to
detect and recover from an aborted DMA transfer.
When a transfer is aborted, any transaction
currently underway will be completed.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 227