PIC32MX440F256H-80I Datasheet, PDF (351/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

14.3.3 16-BIT SYNCHRONOUS EXTERNAL
CLOCK COUNTER/TIMER MODE
In this mode, the timer clock source is an external clock
source or pulse applied to the TxCK pin, TCS
(TxCON<1>) = 1. The 16-bit TMRx Count register
increments on every rising edge of an external clock
when the timer clock prescale <TCKPS> is 1:1.
Note: TxCK pins not available on 64-pin devices.
The timer generates a timer match event after the
TMRx Count register matches the PRx register value,
then resets to 0x0000 on the next external clock cycle.
The timer continues to increment and repeat the period
match until the timer is disabled. For further details
regarding timer events and interrupts, see
Section 14.4 Timer Interrupts.
For clock prescale = N (other than 1:1), the timer
operates at a clock rate = (external clock/N); there-
fore, the TMRx Count register increments on every
Nth external clock cycle. For further details regarding
the timer prescaler, refer to Section 14.3.9 Timer
Clock Prescaler.
The following steps should be performed to properly
configure the timer peripheral for Synchronous Counter
mode operation:
1. Clear control bit, ON (TxCON<15>) = 0, to
disable timer.
2. Select the desired timer prescaler using bits,
TCKPS<2:0> (TxCON<6:4).
3. Set control bit, TCS (TxCON<1>) = 1, to select
an external clock source.
4. Clear Timer register, TMRx.
5. Load Period register, PRx, with desired 16-bit
match value.
6. If timer interrupts are used, refer to Section 14.4
Timer Interrupts for interrupt configuration
steps.
7. Set control bit, ON (TxCON<15>) = 1, to enable
timer.
EXAMPLE 14-2:
T3CON = 0x0;
16-BIT SYNCHRONOUS
EXTERNAL CLOCK
COUNTER/TIMER
INITIALIZATION
//Stop and Init Timer
T3CONSET = 0x0072; //Prescaler=1:256,
//external clock
TMR3 = 0x0;
//Clear timer register
PR3 = 0x3FFF;
//Load period register
T3CONSET = 0x8000;//Start Timer
PIC32MX3XX/4XX
14.3.4 16-BIT GATED CLOCK COUNTER/
TIMER MODE
In this mode, the timer clock source can only be the
internal PBCLK (Peripheral Bus Clock), TCS
(TxCON<1>) = 0. The TxCK pin provides the gating
mechanism to enable and disable the timer counting,
TGATE (TxCON<7>) = 1. The 16-bit TMRx Count reg-
ister is enabled on the rising edge of the TxCK pin and
increments on every internal PBCLK cycle when the
timer clock prescale <TCKPS> is 1:1.
Note: TxCK pins not available on 64-pin devices.
The timer increments until the TMRx Count register
matches the PRx register value. The TMRx Count reg-
ister resets to 0x0000 on the next PBCLK clock cycle.
A timer match event is not generated. The timer contin-
ues to increment and repeat the period match until the
falling edge of the TxCK pin or the timer is disabled. On
the falling edge of the gate signal, a timer gate event is
generated and the TMRx Count register stops count-
ing, but is not reset to 0x0000. The TMRx Count regis-
ter must be reset in software. For further details
regarding timer events and interrupts, see
Section 14.4 Timer Interrupts.
For clock prescale = N (other than 1:1), the timer oper-
ates at a clock rate = (PBCLK/N); therefore, the TMRx
Count register increments on every Nth PBCLK clock
cycle. For further details regarding timer prescaler,
refer to Section 14.3.9 Timer Clock Prescaler.
The following steps should be performed to properly
configure the timer peripheral for Gated Timer mode
operation:
1. Clear control bit, ON (TxCON<15>) = 0, to
disable Timer.
2. Select the desired timer prescaler using bits,
TCKPS<2:0> (TxCON<6:4>).
3. Set control bit, TCS (TxCON<1>) = 0, to select
the internal clock source.
4. Set control bit, TGATE (TxCON<7>) = 1.
5. Clear Timer register, TMRx.
6. Load Period register, PRx, with desired 16-bit
match value.
7. If timer interrupts are to be used, refer to
Section 14.4 Timer Interrupts for interrupt
configuration steps.
8. Set control bit, ON (TxCON<15>) = 1, to enable
timer.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 349