PIC32MX440F256H-80I Datasheet, PDF (393/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
17.2.2 MASTER MODE
In Master mode, data from the SPIxBUF register is
transmitted synchronously on the SDO (output) pin
while synchronous data is received from the slave
device on the SDI (input) pin. In this mode, the Master
controls the synchronous data transfer with the SCK
clock pin by generating 8, 16 or 32 clock pulses,
depending on the selected data size.
17.2.2.1 Master Mode Operations
In Master mode the SCK and SDO pins are outputs and
the SDI pin is an input. Setting the control bit, DISSDO
(SPIxCON<12>), disables transmission at the SDO pin
if Receive Only mode of operation is desired. Refer to
Table 17-7.
The SDI (input) must be configured to properly sample
the data received from the slave device by configuring
the sample bit, SMP (SPIxCON<9>).
In Master mode, the SCK clock edge and polarity must
be configured properly for the master and slave device
to correctly transfer data synchronously. Refer to the
timing diagram shown in Figure 17-3 to determine the
appropriate settings.
In Master mode, the data transfers can be 8, 16, or 32
bits and are configured using control bits,
MODE<32,16> (SPIxCON<11:10>). Refer to Section
17.2.1 “8, 16, and 32-bit Operation”.
In Master mode, the system clock is divided and then
used as the serial clock. The division is based on the
settings in the SPIxBRG register. Refer to
Section 17.2.5 “SPI Master Mode Clock Fre-
quency”.
17.2.2.2 Master SPIxCON Configuration
The following bits must be configured as shown for the
Master mode of operation when configuring the
SPIxCON register:
• Enable Master Mode
MSTEN (SPIxCON<5>) = 1.
• Disable Framed SPI support
FRMEN (SPIxCON<31>) = 0
The remaining bits are shown with example
configurations and may be configured as desired:
• Enable module control of SDO pin – DISSDO
(SPIxCON<12>) = 0
• Configure SCK clock polarity to idle high –
CKP (SPIxCON<6>) = 1
• Configure SCK clock edge transition from Idle to
active – CKE (SPIxCON<8>) = 0
• Select 16-bit data width –
MODE<32,16> (SPIxCON<11:10>) = 01
• Sample data input at middle –
SMP (SPIxCON<9>) = 0
• Enable SPI module when CPU idle –
SIDL (SPIxCON<13>) = 0
17.2.2.3 Master Mode Initialization
The following steps should be performed to setup the
SPI module for the Master mode of operation:
1. If interrupts are used, disable the SPI interrupts
in the respective IEC0/1 register.
2. Stop and reset the SPI module by clearing the
ON bit.
3. Clear the receive buffer.
4. If interrupts are used, the following additional
steps are performed:
• Clear the SPIx interrupt flags/events in the
respective IFS0/1 register.
• Set the SPIx interrupt enable bits in the
respective IEC0/1 register.
• Write the SPIx interrupt priority and subprior-
ity bits in the respective IPC5/7 register.
5. Write the Baud Rate register, SPIxBRG.
6. Clear the SPIROV bit (SPIxSTAT<6>).
7. Write the selected configuration settings to the
SPIxCON register.
8. Enable SPI operation by setting the ON bit
(SPIxCON<15>).
9. Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
Note 1: When using the Slave Select mode, the
SSx or another GPIO pin is used to con-
trol the slave’s SSx input. The pin must
be controlled in software.
2: The user must turn off the SPI device
prior to changing the CKE or CKP bits.
Otherwise, the behavior of the device is
not ensured.
3: The SPI device must be turned off prior to
changing the mode from Slave to Master.
4: The SPIxSR register cannot be written to
directly by the user. All writes to the
SPIxSR register are performed through
the SPIxBUF register.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 391