PIC32MX440F256H-80I Datasheet, PDF (507/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

22.3.4
SYNCHRONIZING ADC
OPERATIONS TO INTERNAL OR
EXTERNAL EVENTS
The modes where an external event trigger pulse ends
sampling
and
starts
conversion
(SSRC2:SSRC0 = 001, 010 or 011) may be used in
combination with auto-sampling (ASAM = 1) to cause
the ADC to synchronize the sample conversion events
to the trigger pulse source. For example, where
SSRC = 010 and ASAM = 1, the ADC will always end
sampling and start conversions synchronously with the
timer compare trigger event. The ADC will have a
sample conversion rate that corresponds to the timer
comparison event rate.
22.3.5 SELECTING AUTOMATIC OR
MANUAL SAMPLING
Sampling can be started manually or automatically
when the previous conversion is complete.
22.3.5.1 Manual
Clearing the ASAM (AD1CON1<2>) bit disables the
Auto-Sample mode. Acquisition will begin when the
SAMP (AD1CON1<1>) bit is set by software. Acquisi-
tion will not resume until the SAMP bit is once again
set.
22.3.5.2 Automatic
Setting the ASAM (AD1CON1<2>) bit enables the
Auto-Sample mode. In this mode, the sampling will
start automatically after the pervious sample has been
converted.
22.3.6 SELECTING THE VOLTAGE
REFERENCE SOURCE
The user can select the voltage reference for the ADC
module. The reference can be internal or external.
The VCFG<2:0> control bits (AD1CON2<15:13>)
select the voltage reference for A/D conversions. The
upper voltage reference (VR+) and the lower voltage
reference (VR-) may be the internal AVDD and AVSS
voltage rails, or the VREF+ and VREF- input pins.
22.3.7 SELECTING THE SCAN MODE
The ADC module has the ability to scan through a
selected vector of inputs. The CSCNA bit
(AD1CON2<10>) enables the MUX A input to be
scanned across a selected number of analog inputs.
PIC32MX3XX/4XX
22.3.7.1 Scan Mode Enable
Scan mode is enabled by setting CSCNA
(AD1CON2<10>). When Scan mode is enabled, the
positive input of MUX A is controlled by the contents of
the AD1CSSL register. Each bit in the AD1CSSL
register corresponds to an analog input. Bit 0 corre-
sponds to AN0, bit 1 corresponds to AN1 and so on. If
a particular bit in the AD1CSSL register is ‘1’, the
corresponding input is part of the scan sequence.
22.3.7.2 Using Scan and Alternate Modes
Together
The Scan and Alternate modes may be combined to
allow a vector of inputs to be scanned and a single
input to be converted every other sample.
This mode is enabled by setting the CSCNA bit = 1,
and setting the ALTS (AD1CON2<0>) bit = 1.
The CSCNA bit enables the scan for MUX A, and the
CH0SB<3:0> (AD1CHS<27:24>) and CH0NB
(AD1CHS<31>) are used to configure the inputs to
MUX B. Scanning only applies to the MUX A input
selection. The MUX B input selection, as specified by
CH0SB<3:0>, will still select a single input.
22.3.8 SETTING THE NUMBER OF
CONVERSIONS PER INTERRUPT
The SMPI<3:0> bits (AD1CON2<5:2>) select how
many A/D conversions will take place before a CPU
interrupt is generated. This also defines the number of
locations that will be written in the result buffer stating
with ADC1BUF0 (ADC1BUF0 or ADC1BUF8 for Dual
Buffer mode). This can vary from 1 sample to 16 sam-
ples (1 to 8 samples for Dual Buffer mode). After the
interrupt is generated, the sampling sequence restarts;
with the result of the first sample being written to the
first buffer location.
The data in the result registers will be overwritten by the
next sampling sequence. The data in the result buffer
must be read before the completion of the first sample
after the interrupt is generated.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 505