PIC32MX440F256H-80I Datasheet, PDF (292/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
11.7 Module Initialization
This section describes the steps that must be taken to
properly initialize the OTG USB module.
11.7.1 ENABLING THE USB HARDWARE
In order to use the USB peripheral, software must set
the USBPWR bit (U1PWRC<0>) to ‘1’. This may be
done in start-up boot sequence.
USBPWR is used to initiate the following actions:
• Start the USB clock
• Allow the USB interrupt to be activated
• Select USB as the owner of the necessary IO pins
• Enable the USB transceiver
• Enable the USB comparators
The USB module and internal registers are reset when
USBPWR is cleared. Consequently, the appropriate ini-
tialization process must be performed whenever the
USB module is enabled, as described in the following
subsections. Otherwise, any configuration packet sent
to the USB module will be stalled, by hardware, until the
reset is complete.
11.7.2 INITIALIZING THE BDT
All descriptors for a given endpoint and direction must
be initialized prior to enabling the endpoint (for that
direction). After a Reset, all endpoints are disabled and
start with the EVEN buffer for transmit and receive
directions.
Transmit descriptors must be written with the UOWN bit
cleared to ‘0’ (owned by software). All other transmit
descriptor setup may be performed anytime prior to
setting the UOWN bit to ‘1’.
Receive descriptors must be fully initialized to receive
data. This means that memory must be reserved for
received packet data. The pointer to that memory
(physical address), and the size reserved in bytes,
must be written to the descriptor. The receive descrip-
tor UOWN bit should be initialized to ‘1’ (owned by
hardware). The DTS and STALL bits should also be
configured appropriately.
If a transaction is received and the descriptor’s UOWN
bit is ‘0’ (owned by software), the USB module returns
a NAK handshake to the host. Usually, this causes the
host to retry the transaction.
11.7.3 USB ENABLE/MODE BITS
USB mode of operation is controlled by the following
enable bits: OTGEN (U1OTGCON<2>), HOSTEN
(U1CON<3>), and USBEN/SOFEN (U1CON<0>).
• OTGEN:
OTGEN selects whether the PIC32MX is to act
as an OTG part (OTGEN = 1) or not. OTG
devices support SRP and HNP in hardware with
Firmware management and have direct control
over the data-line pull-up and pull-down resis-
tors.
• HOSTEN:
HOSTEN controls whether the part is acting in
the role of USB Host (HOSTEN = 1) or USB
Device (HOSTEN = 0). Note that this role may
change dynamically in an OTG application.
• USBEN/SOFEN:
USBEN controls the connection to USB when
the USB module is not configured as a host.
If the USB module is configured as a host,
SOFEN controls whether the host is active on
the USB link and sends SOF tokens every 1 ms.
Note:
The other USB module control registers
should be properly initialized before
enabling USB via these bits.
11.8 Device Operation
All communication on the USB is initiated by the host.
Therefore, in Device mode, when USB is enabled
USBEN = 1 (U1CON<0>), Endpoint 0 must be ready to
receive control transfers. Initialization of the remaining
endpoints, descriptors, and buffers can be delayed until
the host selects a configuration for the device. Refer to
Chapter 9 of the “Universal Serial Bus Specification,
Revision 2.0” for more information on this subject.
The following steps are performed to respond to a USB
transaction:
1. Software pre-initializes the appropriate BDs,
and sets the UOWN bits to ‘1’ to be ready for a
transaction.
2. Hardware receives a TOKEN PID (IN, OUT,
SETUP) from the USB host, and checks the
appropriate BD.
3. If the transaction will be transmitted (IN), the
module reads packet data from data memory.
4. Hardware receives a DATA PID (DATA0/1), and
sends or receives the packet data.
5. If a transaction is received (SETUP, OUT), the
module writes packet data to data memory.
DS61143E-page 290
Preliminary
© 2008 Microchip Technology Inc.