PIC32MX440F256H-80I Datasheet, PDF (361/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 15-1: ICXCON: INPUT CAPTURE X CONTROL REGISTER
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 31
bit 24
r-x
—
bit 23
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
bit 16
R/W-0
R/W-0
R/W-0
r-x
r-x
r-x
R/W-0
R/W-0
ON
FRZ
SIDL
—
—
—
ICFEDGE
ICC32
bit 15
bit 8
R/W-0
ICTMR
bit 7
R/W-0
R/W-0
ICI<1:0>
R-0
ICOV
R-0
ICBNE
R/W-0
R/W-0
ICM<2:0>
R/W-0
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-16
bit 15
bit 14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6-5
Reserved: Write ‘0’; ignore read
ON: ON bit
1 = Module enabled
0 = Disable and Reset module, disable clocks, disable interrupt generation, and allow SFR
modifications
FRZ: Freeze in Debug Mode Control bit
1 = Freeze module operation when in Debug mode
0 = Do not freeze module operation when in Debug mode
Note: FRZ is writable in Debug Exception mode only, it is forced to ‘0’ in normal mode.
SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
Reserved: Write ‘0’; ignore read
ICFEDGE: First Capture Edge Select bit (only used in mode 6, ICxM = 110)
1 = Capture rising edge first
0 = Capture falling edge first
ICC32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
ICTMR: Timer Select bit (Does not affect timer selection when ICxC32 (ICxCON<8>) is ‘1’)
0 = Timer3 is the counter source for capture
1 = Timer2 is the counter source for capture
ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 359