PIC32MX440F256H-80I Datasheet, PDF (530/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
23.4 Power-Saving Operation
Note:
In this data sheet, a distinction is made
between a power mode as it is used in a
specific module, and a power mode as it is
used by the device, e.g., Sleep mode of
the Comparator and SLEEP mode of the
CPU. To indicate which type of power
mode is intended, uppercase and lower-
case letters (Sleep, Idle, Debug) signify a
module power mode, and all uppercase
letters (SLEEP, IDLE, DEBUG) signify a
device power mode.
The purpose of all power saving is to reduce power
consumption by reducing the device clock frequency.
To achieve this, low-frequency clock sources can be
selected. In addition, the peripherals and CPU can be
halted or disabled to further reduce power consump-
tion.
23.5 SLEEP Mode
SLEEP mode has the lowest power consumption of
the device Power-Saving operating modes. The CPU
and most peripherals are halted. Select peripherals
can continue to operate in SLEEP mode and can be
used to wake the device from SLEEP. See the individ-
ual peripheral module sections for descriptions of
behavior in Sleep.
SLEEP mode includes the following characteristics:
• The CPU is halted.
• The system clock source is typically shut down.
See Section 23.5.1 “Oscillator Shutdown In
Sleep Mode” for specific information.
• There can be a wake-up delay based on the
oscillator selection (refer to Table 23-2).
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode.
• The BOR circuit, if enabled, remains operative
during SLEEP mode.
• The WDT, if enabled, is not automatically cleared
prior to entering SLEEP mode.
• Some peripherals can continue to operate in
SLEEP mode. These peripherals include I/O pins
that detect a change in the input signal, WDT,
ADC, UART, and peripherals that use an external
clock input or the internal LPRC oscillator, e.g.,
RTCC and Timer 1.
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
SLEEP.
• The USB module can override the disabling of the
POSC or FRC. Refer to the USB section for spe-
cific details.
• Some modules can be individually disabled by
software prior to entering SLEEP in order to fur-
ther reduce consumption.
The processor will exit, or ‘wake-up’, from SLEEP on
one of the following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset.
• On a WDT time-out. See Section 23.10 “Wake-
Up from SLEEP or IDLE on Watchdog Time-
Out (NMI)”.
If the interrupt priority is lower than or equal to current
priority, the CPU will remain halted, but the PBCLK will
start running and the device will enter into IDLE mode.
Refer Example 23-1 for example code.
Note: There is no FRZ mode for this module.
DS61143E-page 528
Preliminary
© 2008 Microchip Technology Inc.