PIC32MX440F256H-80I Datasheet, PDF (343/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
TABLE 14-1: TIMER2 SFR SUMMARY
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
BF80_0800 T2CON 31:24
23:16
15:8
7:0
BF80_0804 T2CONCLR 31:0
BF80_0808 T2CONSET 31:0
—
—
ON
TGATE
—
—
—
—
—
—
—
—
—
—
—
—
FRZ
SIDL
—
—
—
—
TCKPS<2:0>
T32
—
TCS
Write clears selected bits in T2CON, read yields undefined value
Write sets selected bits in T2CON, read yields undefined value
BF80_080C T2CONINV 31:0
BF80_0810 TMR2 31:24
—
23:16
—
Write inverts selected bits in T2CON, read yields undefined value
—
—
—
—
—
—
—
—
—
—
—
—
BF80_0814 TMR2CLR
15:8
7:0
31:0
TMR2<15:8>
TMR2<7:0>
Write clears selected bits in TMR2, read yields undefined value
BF80_0818 TMR2SET 31:0
BF80_081C TMR2INV 31:0
BF80_0820 PR2 31:24
—
23:16
—
Write sets selected bits in TMR2, read yields undefined value
Write inverts selected bits in TMR2, read yields undefined value
—
—
—
—
—
—
—
—
—
—
—
—
BF80_0824 PR2CLR
15:8
7:0
31:0
PR2<15:8>
PR2<7:0>
Write clears selected bits in PR2, read yields undefined value
BF80_0828 PR2SET 31:0
BF80_082C PR2INV 31:0
Write sets selected bits in PR2, read yields undefined value
Write inverts selected bits in PR2, read yields undefined value
Bit
24/16/8/0
—
—
—
—
—
—
—
—
TABLE 14-2: TIMER2 INTERRUPT REGISTER SUMMARY⁽¹⁾
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
BF88_1060 IEC0
15:8 INT3IE OC3IE
IC3IE
T3IE
INT2IE OC2IE
IC2IE
T2IE
BF88_1030 IFS0
15:8 INT3IF OC3IF
IC3IF
T3IF
INT2IF OC2IF
IC2IF
T2IF
BF88_10B0 IPC2
7:0
—
—
—
T2IP<2:0>
T2IS<1:0>
Note 1: This summary table contains partial register definitions that only pertain to the Timer2 peripheral. Refer to the “PIC32MX Fam-
ily Reference Manual” (DS61132) for a detailed description of these registers.
TABLE 14-3: TIMER3 SFR SUMMARY
Virtual
Address
Name
Bit
Bit
Bit
Bit
Bit
Bit
Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
BF80_0A00 T3CON 31:24
23:16
15:8
7:0
BF80_0A04 T3CONCLR 31:0
BF80_0A08 T3CONSET 31:0
BF80_0A0C T3CONINV 31:0
BF80_0A10 TMR3 31:24
23:16
15:8
7:0
BF80_0A14 TMR3CLR 31:0
BF80_0A18 TMR3SET 31:0
BF80_0A1C TMR3INV 31:0
—
—
ON
TGATE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FRZ
SIDL
—
—
—
—
TCKPS<2:0>
—
—
TCS
Write clears selected bits in T3CON, read yields undefined value
Write sets selected bits in T3CON, read yields undefined value
Write inverts selected bits in T3CON, read yields undefined value
—
—
—
—
—
—
—
—
—
—
—
—
TMR3<15:8>
TMR3<7:0>
Write clears selected bits in TMR3, read yields undefined value
Write sets selected bits in TMR3, read yields undefined value
Write inverts selected bits in TMR3, read yields undefined value
Bit
24/16/8/0
—
—
—
—
—
—
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 341