PIC32MX440F256H-80I Datasheet, PDF (98/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
REGISTER 6-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER
r-x
r-x
r-x
r-x
r-x
R/W-0
r-x
—
—
—
—
—
BMX-
—
CHEDMA
bit 31
r-x
—
bit 24
r-x
r-x
—
—
bit 23
r-x
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
BMXERRIXI BMXER-
BMX-
BMX- BMXERRIS
RICD
ERRDMA ERRDS
bit 16
r-x
r-x
r-x
r-x
r-x
r-x
r-x
r-x
—
—
—
—
—
—
—
—
bit 15
bit 8
r-x
R/W-1
r-x
r-x
r-x
R/W-0
R/W-0
R/W-0
—
BMXWS-
—
—
—
DRM
BMXARB<2:0>
bit 7
bit 0
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
P = Programmable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = Unknown)
r = Reserved bit
bit 31-27
bit 26
bit 25-21
bit 20
bit 19
bit 18
bit 17
bit 16
bit 15-7
Reserved: Write ‘0’; ignore read
BMXCHEDMA: BMX PFM Cacheability for DMA Accesses bit
1 = Enable program Flash memory (data) cacheability for DMA accesses
(requires cache to have data caching enabled)
0 = Disable program Flash memory (data) cacheability for DMA accesses
(hits are still read from the cache, but misses do not update the cache)
Reserved: Write ‘0’; ignore read
BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS: Bus error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction
access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction
access
Reserved: Write ‘0’; ignore read
DS61143E-page 96
Preliminary
© 2008 Microchip Technology Inc.