PIC32MX440F256H-80I Datasheet, PDF (523/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

23.0 POWER SAVING
Note:
This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices. It
is not intended to be a comprehensive refer-
ence source. Refer to the “PIC32MX Family
Reference Manual” (DS61132) for a
detailed description of this peripheral.
This section describes power saving for the
PIC32MX3XX/4XX. The PIC32MX devices offer a total
of nine methods and modes that are organized into two
categories that allow the user to balance power con-
sumption with device performance. In all of the meth-
ods and modes described in this section, power saving
is controlled by software.
23.1 Power Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency, lower-
ing the PBCLK, and by individually disabling modules.
These methods are grouped into the following catego-
ries:
• FRC RUN mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC RUN mode: the CPU is clocked from the
LPRC clock source.
• SOSC RUN mode: the CPU is clocked from the
SOSC clock source.
• Peripheral Bus Scaling mode:
Peripherals are clocked at programmable fraction
of the CPU clock (SYSCLK).
PIC32MX3XX/4XX
23.2 CPU Halted Methods
The device supports two power-saving modes, SLEEP
and IDLE, both of which halt the clock to the CPU.
These modes operate with all clock sources, as listed
below:
• POSC IDLE Mode: the system clock is derived
from the POSC. The system clock source
continues to operate.
Peripherals continue to operate, but can
optionally be individually disabled.
• FRC IDLE Mode: the system clock is derived from
the FRC with or without postscalers.
Peripherals continue to operate, but can option-
ally be individually disabled.
• SOSC IDLE Mode: the system clock is derived
from the SOSC.
Peripherals continue to operate, but can
optionally be individually disabled.
• LPRC IDLE Mode: the system clock is derived from
the LPRC.
Peripherals continue to operate, but can option-
ally be individually disabled. This is the lowest
power mode for the device with a clock running.
• SLEEP Mode: the CPU, the system clock source,
and any peripherals that operate from the system
clock source, are halted.
Some peripherals can operate in SLEEP using
specific clock sources. This is the lowest power
mode for the device.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 521