PIC32MX440F256H-80I Datasheet, PDF (73/646 Pages) Microchip Technology – 64/100-Pin General Purpose and USB 32-Bit Flash Microcontrollers

PIC32MX3XX/4XX
4.2.1.1 Primary Oscillator (POSC)
The POSC has six operating modes, as summarized in
Table 4-6. The first three modes can each be combined
with a PLL module to form the last three modes.
Figure 4-2, Figure 4-3, and Figure 4-4 show various
POSC configurations. The primary oscillator is con-
nected to the OSCI and OSCO pins of the device fam-
ily. The primary oscillator can be configured for an
external clock input, or an external crystal or resonator.
The XT, XTPLL, HS, and HSPLL modes are External
Crystal or Resonator Controller Oscillator modes. The
XT and HS modes are functionally very similar. The pri-
mary difference is the gain of the internal inverter of the
oscillator circuit (see Figure 4-2). The XT mode is a
medium-power, medium-frequency mode and has
medium inverter gain. HS mode is higher power and
provides the highest oscillator frequencies and has the
highest inverter gain. OSCO provides crystal/resonator
feedback in both XT and HS Oscillator modes and
hence is not available for use as a input or output in
these modes. The XTPLL and HSPLL modes have a
Phase Locked Loop (PLL) with user selectable input
divider, multiplier, and output divider to provide a wide
range of output frequencies. The oscillator circuit will
consume more current when the PLL is enabled.
The External Clock modes, EC and ECPLL, allow the
system clock to be derived from an external clock
source. These modes configure the OSCI pin as a
high-impedance input that can be driven by a CMOS
driver. The external clock can be used to drive the sys-
tem clock directly (EC) or the ECPLL module with pres-
cale and postscaler can be used to change the input
clock frequency (ECPLL). The External Clock modes
also disable the internal feedback buffer, allowing the
OSCO pin to be used for other functions. In External
Clock mode, the OSCO pin can be used as an addi-
tional device I/O pin (see Figure 4-4) or as a PBCLK
output pin (see Figure 4-3).
Note:
When using PLL modes, the input divider
must be chosen such that the resulting
frequency applied to the PLL is in the
range of 4 MHz to 5 MHz.
TABLE 4-6: PRIMARY OSCILLATOR OPERATING MODES
Oscillator Mode Description
HS
10 MHz-40 MHz crystal
XT
3.5 MHz-10 MHz resonator
EC
External clock input (0-80 MHz)
HSPLL
10 MHz-40 MHz crystal, PLL enabled
XTPLL
4 MHz-10 MHz resonator, PLL enabled
ECPLL
External clock input (5-80 MHz), PLL enabled
Note: The clock applied to the CPU after applicable prescalers, postscalers, and PLL multipliers must not exceed
the maximum allowable processor frequency.
FIGURE 4-2:
CRYSTAL OR CERAMIC RESONATOR OPERATION (XT, XTPLL, HS, OR HSPLL
OSCILLATOR MODE)
C1⁽³⁾
C2⁽³⁾
OSCI
XTAL
OSCO
RS⁽¹⁾
To Internal Logic
RF⁽²⁾
Enable
PIC32MX3XX/4XX
Note 1:
2:
3:
A series resistor, Rs, may be required for AT strip cut crystals.
The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
Refer to the “PIC32MX Family Reference Manual” (DS61132) for help determining the best oscillator components.
© 2008 Microchip Technology Inc.
Preliminary
DS61143E-page 71